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Rev 2; 1/09
5-Cell to 10-Cell Li+ Protector with Cell Balancing
General Description
The DS2726 provides full charge and discharge protection for 5- to 10-cell lithium-ion (Li+) battery packs. The protection circuit monitors individual cell voltages to detect overvoltage and undervoltage conditions. Protection against discharge overcurrent and short-circuit current is provided with user-selectable thresholds using external resistors. P-channel protection FETs are employed high side and driven from on-chip 10V FET drivers. Cell balancing can be enabled to ensure that all cells are equally charged. Pin Programmable for 5 to 10 Cells Internal Cell-Balancing Circuit, Shunts Up to 300mA Pin-Programmable VOV Threshold Pin-Programmable Cell-Balance Voltage Overdischarge Current and Short-Circuit Current Set with External Resistors Overdischarge Current and Short-Circuit Current Timeout Delay Set with External Capacitors Low Power Consumption: 60A (typ) Low Shutdown Power Consumption: 5A (typ) 7mm x 7mm, 32-Pin TQFN Lead-Free Package
Features
Complete Protection for 5-Cell to 10-Cell Li+ Packs
DS2726
Applications
Power Tools Electric Bikes Home Appliances
Simplified Typical Application Circuit
PKP+
Ordering Information
PART DS2726G+ DS2726G+T&R TEMP RANGE -20C to +85C -20C to +85C PIN-PACKAGE 32 TQFN-EP* 32 TQFN-EP*
PKP CC VCC VCC
SNS
DC VIN V10
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
V09 SEL0 SEL1 OVS0 OVS1 CBS0 CBS1 CBCFG SLEEP SLEEP V06 V07
V08
DS2726
CSCD
V05
Pin Configuration appears at end of data sheet.
V04
VIN RSC RDOC
V03
V02
CDOCD
V01
V00 GND PKP-
________________________________________________________________ Maxim Integrated Products
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5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V00-V10, PKP, RDOC, RSC Pins Relative to GND .....................-0.3V to +60V Voltage Range on DC Pin Relative to VIN ..............-12V to +0.3V Voltage Range on CC Pin Relative to PKP .............-12V to +0.3V Voltage Range on CSCD, SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP, CBCFG, VCC Pins Relative to GND ...................-0.3V to +6.0V Human Body Model (HBM) ESD Limit of V05-V09, PKP, CC, DC ....................................................500V All Other Pins......................................................................2kV Voltage Range on Any Vx to Vx-1 (V10 to V09).......-0.3V to +12V Continuous Power Dissipation (TA = +70C) 32-Pin, 7mm x 7mm Thin QFN (derate 37mW/C above +70C) ................................2963mW Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -20C to +85C.)
PARAMETER Supply Range Input Range: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, CSCD, CDOCD, SLEEP, CBCFG SYMBOL VIN CONDITIONS (Notes 1, 2, 3, 4) (Note 1) MIN 5 -0.3 TYP MAX 50 VCC + 0.3 UNITS V V
DC ELECTRICAL CHARACTERISTICS
(TA = -20C to +85C.)
PARAMETER Supply Current V00-V10 Leakage Current Input Logic-High: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP Input Logic-Mid: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP Input Logic-Low: SEL0, SEL1, OVS0, OVS1, CBS0, CBS1, SLEEP VCC Output Voltage VCC Dropout Voltage Output Low: CC Output Low: CC Driver Current VOLCC VIH SYMBOL IDD IDD_BAL I SLEEP CONDITIONS Protector mode, no fault (Notes 4, 9) Load balancing (Note 11) Sleep mode All cell voltages = 4.2V (Note 10) ILOAD = 2A (Notes 1, 5) -2 VCC 0.4 5.0 MIN TYP 70 MAX 90 400 7.5 +2 A V A UNITS
VIM
ILOAD = 0 (Notes 1, 5)
1.30
1.65
2.00
V
VIL
ILOAD = -2A (Notes 1, 5) ILOAD = 1mA (Notes 1, 5, 8) (Note 6) I OL = -100A, VPKP CC = V OLCC + 2V CC = V OHCC - 1V 13V (Notes 3, 5) PKP - 12 -3 -15 4.75 5.00
GND + 0.4 5.25 5.5 PKP - 8 -1 -7
V V V V mA
2
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5-Cell to 10-Cell Li+ Protector with Cell Balancing
DC ELECTRICAL CHARACTERISTICS (continued)
(TA = -20C to +85C.)
PARAMETER Output High: CC Output High: CC Driver Current Output Low: DC Output Low: DC Driver Current Output High: DC Output High: DC Driver Current Maximum Balancing Current Balance FET: On-Resistance IBAL IBAL = 180mA 1.7 3.2 VOHDC VOLDC SYMBOL VOHCC I OH = 100A CC = V OLCC + 2V CC = V OHCC - 1V I OL = -100A, VVIN DC = V OLDC + 2V DC = V OHDC - 1V I OH = 100A DC = V OLDC + 2V DC = V OHDC - 1V 13V (Notes 3, 5) CONDITIONS MIN PKP 0.5 7 0.5 VIN 12 -3 -15 VIN 0.5 7 0.5 TYP MAX PKP + 0.3 15 1.5 VIN 8 -1 -7 VIN + 0.3 15 1.5 300 7.0 UNITS V mA V mA V mA mA
DS2726
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT
(TA = 0C to +50C.)
PARAMETER SYMBOL CONDITIONS OVS1 = GND, OVS0 = GND OVS1 = GND, OVS0 = N.C. OVS1 = GND, OVS0 = VCC OVS1 = N.C., OVS0 = GND Overvoltage Detect VOV OVS1 = N.C., OVS0 = N.C. OVS1 = N.C., OVS0 = VCC OVS1 = VCC, OVS0 = GND OVS1 = VCC, OVS0 = N.C. OVS1 = VCC, OVS0 = VCC Charge-Enable Voltage VCE MIN 4.05 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 VOVMIN 0.15 VBAL lowest typical set point limited to 3.75V VOVMIN CellBalancing Threshold 2.7 2.2 VVIN - VRDOC = V VIN - VRSC = 2V 0.95 -3 2.8 2.3 1.00 TYP 4.10 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50 MAX 4.15 4.20 4.25 4.30 4.35 4.40 4.45 4.50 4.55 VOVMAX 0.15 VOVMAX CellBalancing Threshold 2.9 2.4 1.05 +3 V V UNITS
Charge-Balance Voltage
VBAL
V
Undervoltage Release Undervoltage Detect RDOC, RSC Output Current RDOC, RSC Input Offset Voltage
VUVREL VUV
V V A mV
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5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (continued)
(TA = 0C to +50C.)
PARAMETER Overvoltage Delay Undervoltage Delay Discharge Overcurrent Delay Short-Circuit Delay Charger-Detect Threshold (VPKP - VVIN) Test Threshold Test Current SYMBOL t OVD tUVD tDOCD t SCD VCDET VTP ITST DOC conditions DOC condition, VIN - VPKP = 2V DOC condition, VIN - VPKP = 50V CDOCD = 100pF (Notes 7, 12) CDOCD = 1000pF (Notes 7, 12) CSCD = 100pF (Notes 7, 12) CSCD = 1000pF (Notes 7, 12) CONDITIONS MIN 128 x tDOCDMIN 128 x tDOCDMIN 2.56 25.6 45 405 3 0.8 68 0.5 1.2 120 1.20 3.20 32.0 58 508 TYP MAX 128 x tDOCDMAX 128 x tDOCDMAX 3.84 38.4 72 612 17 1.7 200 1.8 UNITS ms ms ms s mV V A mA
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12:
All voltages relative to GND. Voltages below this level cannot be monitored; therefore, CC and DC are off below this value. Full-gate drive is not achieved until the voltage source for the gate driver (VPKP or VVIN) is above 13V. With 10F decoupling capacitor. ILOAD is the current load on the pin specified in the parameter. VCC cannot meet specification if VVIN is below this value. Capacitance tolerance introduces additional error. With 0.1F decoupling capacitor. Current is an average. Spikes up to 200A when measuring cell voltages. Current is an average. Spikes up to 15A when measuring cell voltages. Current depends on the number of cells being balanced. Includes switching time and comparator delay with 25mV overdrive.
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5-Cell to 10-Cell Li+ Protector with Cell Balancing
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DS2726
OV ACCURACY vs. TEMPERATURE
DS2726 toc01
UV ACCURACY vs. TEMPERATURE
DS2726 toc02
TEST CURRENT vs. (VVIN - VPKP)
DS2726 toc03
0.009 0.007 0.005 OV ACCURACY (V)
1.2 1.0 0.8 ITST (mA) 0.6 0.4
0.014 0.012 UV ACCURACY (V) 0.010 0.008 0.006 0.004 0.002 0
0.003 0.001 -0.001 -0.003 -0.005 -0.007 -0.009 -40 -15 10 35 60 85 TEMPERATURE (C)
0.2 0 -40 -15 10 35 60 85 0 10
VTP = 1.16V 20 30 40 50 60
TEMPERATURE (C)
(VVIN - VPKP) (V)
DISCHARGE OVERCURRENT DELAY (CDOCD = 1000pF, RDOC = 110k WITH RDS_ON = 2.75k)
1 -1 VGS DISCHARGE FET (V) LOAD CURRENT LOAD CURRENT (A) -3 -5 -7 VGS DISCHARGE FET -9 -11 0 10 20 30 40 50 TIME (ms) 0 -10 -9 -11 0 DISCHARGE OVERCURRENT THRESHOLD 30 20 10
DS2726 toc04
SHORT-CIRCUIT DELAY (CDOCD = 1000pF, RSC = 247.5k WITH RDS_ON = 2.75M)
50 40 VGS DISCHARGE FET (V) 1 SHORT-CIRCUIT CONDITION -1 -3 LOAD CURRENT -5 -7 SHORT-CIRCUIT THRESHOLD VGS DISCHARGE FET 60 40 20 0 50 TIME (s) 100 100 80 LOAD CURRENT (A)
DS2726 toc05
DOC CONDITION
120
FET TURN-OFF TIME (WITH 460nC TOTAL GATE CHARGE)
40 35 30 25 5V/div 20 15 10 5 20 40 60 80 100 120 140 160 180 200 20s/div
DS2726 toc06
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5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
PKP+
PKP RTST
CC
SNS
DC
VIN
DS2726
10V 10V VOV, VBAL, VCE, VUV V09 VIN VREG VOV, VBAL, VCE, VUV V07 SEL0 SEL1 OVS0 OVS1 LOGIC CBS0 CBS1 CBCFG SLEEP RSC tSCD VIN CSCD RDOC tDOCD VOV, VBAL, VCE, VUV CDOCD SNS V00 VOV, VBAL, VCE, VUV V01 VOV, VBAL, VCE, VUV V02 VOV, VBAL, VCE, VUV V03 VOV, VBAL, VCE, VUV V04 VOV, VBAL, VCE, VUV V05 VOV, VBAL, VCE, VUV V06 VCDET VOV, VBAL, VCE, VUV V08 V10
VCC
VCC
GND PKP-
Figure 1. Block Diagram
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5-Cell to 10-Cell Li+ Protector with Cell Balancing
Pin Description
PIN 1 2 3 NAME RSC RDOC VCC SEL0, SEL1 CDOCD FUNCTION Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for a short-circuit condition in the discharge direction. Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack selects the threshold voltage for an overcurrent condition in the discharge direction. Regulator Supply Output. VCC supplies power to internal circuits and can be used to pull configuration pins to VIH. It should be bypassed to GND with at least a 0.1F ceramic capacitor. Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 2 for how to drive this pin for a particular number of cells. Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a discharge overcurrent condition must persist before shutting off the DC FET. Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state. The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this pin enables cell balancing. Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time for which a short-circuit current condition must persist before shutting off the DC FET. Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if VPKP > VVIN + VCDET. When this pin is at a logic-high, charge balancing is enabled if the SLEEP pin is at a logic-high. Select Cell-Balancing Voltage. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to drive this pin for a particular cell-balancing voltage threshold. Select Overvoltage Threshold. This input is a three-level input. Connect to ground or VCC for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to drive this pin for a particular overvoltage threshold. No Connection. Not internally connected. Ground. Connect to the negative terminal of the lowest voltage cell. Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack. Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack. Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack. Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack. Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack. Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack. Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack. Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack. Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack. Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack. Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack. Connect to the Most Positive Cell Terminal Discharge Control Output. DC controls the gate of the discharge FET. Driven from VIN to V OLDC to turn on and turn off the discharge FET.
DS2726
4, 5
6
7
SLEEP
8
CSCD
9
CBCFG
10, 11
CBS0, CBS1 OVS0, OVS1 N.C. GND V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 VIN DC
12, 13 14, 30 15 16 17 18 19 20 21 22 23 24 25 26 27 28
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5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
Pin Description (continued)
PIN 29 31 32 -- NAME SNS CC PKP EP FUNCTION Sense Input. Connect to the drains of the charge and discharge FETs. Used as a voltage reference for detecting short-circuit and discharge overcurrent conditions. Charge Control Output. CC controls the gate of the charge FET. Driven from PKP to VOLCC to turn on and turn off the charge FET. Pack Positive. The voltage on PKP is used to detect charger-attach and protection-release conditions. Exposed Pad Ground. Connect to the negative terminal of the lowest voltage potential cell.
PKP+ 15 VIN 150
150 150
1F 150 150 1F 10F V10 V09 V08 N.C. V10 PKP SNS
150k VCC 60V 1A 82.5k 205k V09 CC DC VIN 0.1F 1k 0.1F 1k 1k 1k 1k 1k
V07 V06 V05 V04 V03 V02
1k SLEEP
10k
RSC RDOC VCC SEL0 SEL1 CDOCD SLEEP CSCD CBCFG CBS0 CBS1
V08 V07 V06 V05
DS2726
V04 V03 V02 V01
OVS0
OVS1
6.2V 1F V01 V00 PKP-
Figure 2. Typical Application Circuit
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V00
1F
GND
N.C.
5-Cell to 10-Cell Li+ Protector with Cell Balancing
Detailed Description
The DS2726 provides the protection features for a 5-cell to 10-cell Li+ battery pack. The Li+ protection circuit allows for pin-configured selection of OV threshold and the cell-balancing threshold. DOC and SC thresholds and delays are component programmable. overvoltage. Then the IC begins controlling the CC and DC FETs as shown in Table 1. Care should be taken to ensure that the SLEEP pin is not held low during a wake condition.
DS2726
Charger Detect
The DS2726 has two different methods for detecting a charger connection. The methods are pin programmable at the CBCFG pin. If CBCFG is pulled to GND, then charge detection occurs when VPKP > VVIN + VCDET. If CBCFG is pulled to VCC, then charge detection occurs when the SLEEP pin is driven to a logic-high state.
Sleep Mode
Sleep Mode is a low-power state where the FETs are open and the IC is not monitoring voltages. During Wake Mode, the IC measures voltages and drives the FETs to the appropriate state. Upon initial connection to cells, the DS2726 enters Sleep Mode. The IC also enters Sleep Mode if a UV condition is detected. Sleep Mode can be initiated any time by pulling the SLEEP pin low while a chargerdetect condition does not exist. During Sleep Mode there is a pulldown current from PKP to GND. VPKP must be within VTP of VVIN (VPKP > VVIN - VTP) to exit wake from Sleep Mode. When a charger is detected and VCC achieves regulation, the part measures all cells for undervoltage and
Li+ Protection Circuitry
In Active Mode, the DS2726 constantly monitors V00- V10 to protect the battery from overvoltage and undervoltage. The voltage on the SNS pin is monitored and compared to the voltages on RDOC and RSC to protect against excessive discharge currents (discharge overcurrent and short circuit). Table 1 summarizes the conditions that activate the protection circuit, the response of the DS2726, and the thresholds that release it from a protection state.
Table 1. Li+ Protection Conditions and DS2726 Responses
CONDITION* Overvoltage (OV) ACTIVATION THRESHOLD VCELL > V OV DELAY t OVD RESPONSE CC Off RELEASE THRESHOLD VCELL < VCE CBCFG < VIL and VCELL < VUV_REL, then VPKP > VVIN + VCDET (Note 13) Undervoltage (UV) (Note 15) VCELL < VUV tUVD CC Off, DC Off, Sleep Mode CBCFG < VIL and VCELL > VUV_REL, then VPKP > VVIN - VTP CBCFG > VIH then SLEEP > VIH and VPKP > VVIN - VTP Discharge Overcurrent (DOC) (Note 15) Short Circuit (SC) VSNS < VRDOC VSNS < VRSC tDOCD t SCD DC Off DC Off VPKP > VVIN - VTP (Note 14) VPKP > VVIN - VTP (Note 15)
*All voltages are with respect to GND. CC Off: VCC = VPKP, DC Off: VDC = VVIN. Note 13: The DC FET remains off until VCELL > VUV_REL. Note 14: With test current ITST flowing from VIN to PKP. Note 15: If a DOC condition persists indefinitely and a UV condition is reached, the IC does not enter Sleep Mode.
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9
5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
Li+ Protection Conditions
Overvoltage, OV. If any cell voltage (VCELL) exceeds the overvoltage threshold, VOV, for a period longer than overvoltage delay, t OVD , the DS2726 shuts off the external charge FET. When V CELL falls below the charge-enable threshold VCE, the DS2726 turns the charge FET on. The discharge FET remains enabled during the overvoltage event. Care should be taken while discharging during an OV condition because the current drawn by the load is going through the body diode of the CC FET. Undervoltage, UV. If VCELL drops below the undervoltage threshold, VUV, for a period longer than undervoltage delay, tUVD, the DS2726 shuts off the charge and discharge FETs and enters Sleep Mode. The device remains in Sleep Mode until a charger is detected, at which point the DS2726 wakes up and enables the CC FET. The DC FET remains disabled until every cell is above the VUV_REL threshold. Care should be taken while charging during a UV event because the charge current is flowing through the body diode of the DC FET. Discharge Overcurrent, DOC. If V SNS is less than VRDOC for a period longer than tDOCD, the DS2726 shuts off the external discharge FET. The discharge current path is not reestablished until VPKP rises above VVIN - VTP. The DS2726 provides a test current of value I TST from the PKP pin to the V IN pin to detect the removal of the offending low-impedance load. ITST is not disabled if an undervoltage condition is reached. Short Circuit, SC. If VSNS is less than VRSC for a period longer than short-circuit delay tSCD, the DS2726 shuts off the external discharge FET. The discharge current path is not reestablished until VPKP rises above VVIN - VTP. The DS2726 provides a test current of value I TST from the PKP pin to the V IN pin to detect the removal of the short. ITST is disabled if an undervoltage condition is reached. Summary. All the protection conditions described are logic ORed to affect the CC and DC outputs: DC = (Undervoltage) or (Discharge Overcurrent) or (Short Circuit) CC = (Overvoltage) or (Undervoltage and Charger Detect)
VCELL
VOV VCE VUV_REL VUV
CHARGE VSNS VVIN VRDOC VRSC VOHCC CC tOVD tOVD tUVD VOLCC VOHDC DC tSCD tOCD tUVD VOLDC POWER MODE ACTIVE SLEEP
DISCHARGE
Figure 3. Li+ Protection Circuitry Example Waveforms
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5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
9 CELLS V10 V10 8 CELLS V10 7 CELLS V10 6 CELLS V10 5 CELLS
V09
V09
V09
V09
V09
V08
V08
V08
V08
V08
V07
V07
V07
V07
V07
V06
V06
V06
V06
V06
V05
V05
V05
V05
V05
V04
V04
V04
V04
V04
V03
V03
V03
V03
V03
V02
V02
V02
V02
V02
V01
V01
V01
V01
V01
V00
V00
V00
V00
V00
Figure 4. Cell Bypassing Connection
Configuration for Number of Cells
The DS2726 protects 5 to 10 Li+-based cells connected in series. The number of cells is configured using the SEL0 and SEL1 pins according to Table 2. Pin V10 should always be connected to the positive terminal of the battery stack regardless of the number of cells in the stack. Cell connections that are not in use for battery stacks with fewer than 10 cells should be shorted to the cell connection below it. For example, a stack with 9 cells would have V9 shorted to V8 and V8
connected to the positive terminal of the 8th cell; a stack with 8 cells would have V9 shorted to V8 shorted to V7 and V7 connected to the positive terminal of the 7th cell, and so on (see Figure 4).
Cell Connection Order
Care must be taken when connecting cells to the DS2726 to avoid damaging the device. GND should be connected first, then VIN. Next, V0 should be connected, then V1 and so on until V10 is connected last.
Table 2. Number of Cells Configuration
PIN SEL0 SEL1 NUMBER OF SERIES-CONNECTED CELLS 5 VIL VIL 6 VIM VIL 7 VIH VIL 8 VIL VIM 9 VIM VIM 10 VIH VIM 10 VIL VIH 10 VIM VIH 10 VIH VIH
Note: The DC FET remains off until VCELL > VUV_REL. ______________________________________________________________________________________ 11
5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
Configuration of Overvoltage Threshold
The DS2726 allows the OV threshold to be set using the overvoltage select pins. The OV threshold is configured using the OVS0 and OVS1 pins according to Table 3. ancing voltage is never allowed a value below 3.75V. Setting the OVS0 and OVS1 pins low while the CBS0 and CBS1 pins are high results in a cell-balancing voltage (VBAL) of 3.75V. Nominal Cell-Balancing Voltage: VBAL = VOV - Cell-Balancing Voltage Threshold Balancing begins when any cell's voltage is greater than VBAL. When the balancing condition is met and cell balancing is enabled, the corresponding internal FET (from Vx to Vx-1) is enabled, shunting a portion of the charge current around the cell. The external resistors on V00-V10 should be chosen to limit the balancing current to a maximum of 200mA. This prevents damaging the internal cell-balancing FETs. The DS2726 has three distinct states during balancing. A voltage measurement state of 5/32 tOCD time periods is followed by a balancing state where even numbered cells are balanced for 123/32 t OCD time periods. Another voltage measurement state of 5/32 tOCD time periods then occurs. This is followed by a balancing state where odd numbered cells are balanced for 123/32 tOCD time periods. This gives an average balancing current of approximately half the maximum balance current. Cell balancing terminates when all cell voltages are greater than VBAL. See the Measurement Sequence section.
Enabling Cell Balancing
For cell balancing to begin the DS2726 must detect a charger. The charge-balancing configuration pin (CBCFG) controls how the IC detects a charger. If CBCFG is pulled to GND, balancing is enabled when the charge-current comparator detects a charger. This detection occurs when VPKP > VVIN + VCDET. If CBCFG is pulled to VCC, cell balancing is enabled when the SLEEP pin is driven to a logic-high state. Note that cell balancing must be enabled and a valid cell-balancing voltage must exist for cell balancing to occur.
Configuration of Cell-Balancing Voltage Threshold
The DS2726 allows the cell-balancing threshold to be set using the cell-balance select pins. The threshold is configured using the CBS0 and CBS1 pins according to Table 4. Setting the cell-balancing voltage threshold to zero disables the cell-balancing circuitry. The nominal cell-bal-
Table 3. OV Threshold Configuration
PIN OVS0 OVS1 NOMINAL OV THRESHOLD (V) 4.10 VIL VIL 4.15 VIM VIL 4.20 VIH VIL 4.25 VIL VIM 4.30 VIM VIM 4.35 VIH VIM 4.40 VIL VIH 4.45 VIM VIH 4.50 VIH VIH
Table 4. Cell-Balancing Threshold Configuration
PIN CBS0 CBS1 CELL-BALANCING VOLTAGE THRESHOLD (OFFSET FROM V OV) (V) 0.00 VIL VIL 0.05 VIM VIL 0.10 VIH VIL 0.15 VIL VIM 0.20 VIM VIM 0.25 VIH VIM 0.30 VIL VIH 0.35 VIM VIH 0.40 VIH VIH
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5-Cell to 10-Cell Li+ Protector with Cell Balancing
Setting the Short-Circuit Threshold and Delay Time
The DS2726 allows the selection of a short-circuit current threshold. This threshold is set using a resistor from the RSC pin to the positive terminal of the cell stack. The RSC pin sinks 1A (nominal). The short-circuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RSC pin. For example, assume a 500k resistor is used on RSC, along with a DC FET with an RDS_ON of 10m. This corresponds to an RSC voltage of 500k x 1A = 0.5V. Because the FET is 10m, the short-circuit threshold is 0.5V/10m = 50A: I SC = 1A x RSC R DS _ ON rent circuit comparator triggers when the voltage on the SNS pin is less than the voltage on the RDOC pin. For example, assume a 200k resistor is used on RDOC, along with a DC FET with an RDS_ON of 10m. This corresponds to a voltage on RDOC of 200k x 1A = 0.2V. Because the FET is 10m, the discharge overcurrent threshold is 0.2V/10m = 20A: IDOC = 1A x RDOC R DS _ ON
DS2726
The DS2726 allows for a delayed reaction to a short-circuit event. The short threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capacitance of the DC FET; see the DC pin drive capabilities in the DC Electrical Characteristics table for more details). The short-circuit delay time is set using a capacitor on the CSCD pin. The short-circuit delay time can be calculated by the equation: tSCD = CSCD x 500k Be sure to select threshold and delay times that fall within the safe operating area of the FETs chosen for DC and CC.
The DS2726 allows for a delayed reaction to a discharge overcurrent event. The discharge overcurrent threshold must persist for the entire delay time before the DC FET begins to turn off (actual turn-off time varies based on the gate capacitance of the DC FET; see DC pin drive capabilities in the DC Electrical Characteristics table for more details). The discharge overcurrent delay time is set using a capacitor on the CDOCD pin. The discharge overcurrent delay can be calculated by the equation: tDOCD = CDOCD x 32M Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC. If the voltage on the CDOCD pin is within approximately 1V of VCC or GND, the condition is considered to be a fault, and the CC and DC outputs are disabled. This results in a delay before enabling the FETs when the part awakens from Sleep Mode. This delay occurs until the voltage on CDOCD reaches an acceptable level. This is a function of the capacitor on CDOCD. The CDOCD startup delay is in addition to a typical regulator startup of 100s, and is given by the equation: STARTUP DELAY 100s + CDOCD x 1.65M Be sure to select threshold and delay times that fall within the safe operating area for the FETs chosen for DC and CC.
Setting the Discharge Overcurrent Threshold and Delay Time
The DS2726 allows the selection of a discharge overcurrent threshold. This threshold is set using a resistor from the RDOC pin to the positive terminal of the cell stack. The RDOC pin sinks 1A (nominal). The overcur-
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13
5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
Measurement Sequence
The period with which the DS2726 measures voltages is a function of the discharge overcurrent delay time, tDOCD. Figure 5 illustrates the measurement sequence. One measurement period: 4 x tDOCD VUV, VUV_REL, VCE, VOV, and VBAL are measured for all cells: 5 x tDOCD/32 Chip performs balancing on even cells: 123 x tDOCD/32 One measurement period: 4 x tDOCD VUV, VUV_REL, VCE, VOV, and VBAL are measured for all cells: 5 x tDOCD/32 Chip performs balancing on odd cells: 123 x tDOCD/32 One cell-balancing period: 8 x tDOCD
Overvoltage and Undervoltage Delay Time
Cell voltages are measured simultaneously and then sequentially compared to each of the five thresholds VUV, VUV_REL, VCE, VOV, and VBAL. This sequence is repeated every four tDOCD intervals. Overvoltage and undervoltage conditions are time qualified and therefore not recognized immediately. If an overvoltage condition exists on any cell for 32 intervals consecutively (tOVD = 4 x 32 x tDOCD = 128 x tDOCD), an overvoltage condition is recognized, and the CC FET is turned off. If an undervoltage condition exists on any cell for 32 intervals consecutively (tUVD = 4 x 32 x tDOCD = 128 x tDOCD) an undervoltage condition is recognized, the CC and DC FETs are turned off, and Sleep Mode is entered.
ONE CELL-BALANCING PERIOD ONE MEASUREMENT PERIOD tDOCD/ 32 1 tDOCD/ 32 2 tDOCD/ 32 3 tDOCD/ 32 4 tDOCD/ 32 5 tDOCD/ 32 1 tDOCD/ 32 2 tDOCD/ 32 3 ... tDOCD/ 32 123 tDOCD/ 32 1 tDOCD/ 32 2 tDOCD/ 32 3 tDOCD/ 32 4 tDOCD/ 32 5 tDOCD/ 32 1 tDOCD/ 32 2 tDOCD/ 32 3 ... tDOCD/ 32 123
VUV, VUV_REL, VCE, VOV, AND VBAL ARE MEASURED FOR ALL CELLS
CELL BALANCING IS PERFORMED ON EVENNUMBERED CELLS
VUV, VUV_REL, VCE, VOV, AND VBAL ARE MEASURED FOR ALL CELLS
CELL BALANCING IS PERFORMED ON ODDNUMBERED CELLS
1
2
3
4
5
6 ...
32 4 x tDOCD
4 x tDOCD 4 x tDOCD 4 x tDOCD 4 x tDOCD 4 x tDOCD 4 x tDOCD
128 x tDOCD, PART RESPONDS TO VUV, VUV_REL, VCE, VOV, AND VBAL CONDITION
Figure 5. Cell Balancing and Measurement Periods
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5-Cell to 10-Cell Li+ Protector with Cell Balancing
Pin Configuration
V08 V07 V05 V04 V03 V06 V02 V01
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 32 TQFN-EP PACKAGE CODE T3277+2 DOCUMENT NO. 21-0144
DS2726
TOP VIEW
24 V09 25 V10 26 VIN 27 DC 28 SNS 29 N.C. 30 CC 31 PKP 32 1 RSC
23
22
21
20
19
18
17 16 15 14 13 V00 GND N.C. OVS1 OVS0 CBS1 CBS0 CBCFG
DS2726
12 11
+
2 RDOC 3 VCC 4 SEL0 5 SEL1 6 CDOCD
*EP
10 9
7 SLEEP
8 CSCD
TQFN (7mm x 7mm)
*EXPOSED PAD.
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15
5-Cell to 10-Cell Li+ Protector with Cell Balancing DS2726
Revision History
REVISION NUMBER 0 REVISION DATE 4/08 DESCRIPTION PAGES CHANGED
Initial release. * Deleted the "50mV Overvoltage Accuracy" from the Features section. * Added the Cell Connection Order section. * Corrected wording mistake in the Configuration of Cell-Balancing Voltage Threshold section involving minimum cell-balancing voltage configuration. * Corrected PFET drawings in schematics. * Added the PKP, CC, DC pins to the Human Body Model (HBM) ESD Limit in the Absolute Maximum Ratings.
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1
9/08
1, 11, 12
2
1/09
1, 2, 6, 8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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